Business Wire

MathWorks Speeds FPGA and ASIC Verification with Universal Verification Methodology (UVM) Support

NATICK, Mass.--(BUSINESS WIRE)--MathWorks today announced that HDL Verifier provides support for the Universal Verification Methodology (UVM) starting with Release 2019b, which is currently available.
Business Wire

SpringSoft’s Verdi Debug Software Expands Verification Interoperability with Comprehensive UVM Support

HSINCHU, Taiwan--(BUSINESS WIRE)--SpringSoft, Inc., a global supplier of specialized IC design software, today announced comprehensive support for the Universal Verification Methodology (UVM) with its ...
Semiconductor Engineering

UVM Do’s And Don’ts For Effective Verification

With more than a year of production use, the Accellera Systems Initiative UVM is now clearly the methodology of choice for verification. The rush to adopt UVM has both matured the BCL quickly, ...
Semiconductor Engineering

Best Practices In Verification

The advent of advanced verification methodologies such as the UVM and its predecessors VMM and OVM has changed the verification landscape in many ways. Design and verification teams used to worry ...
EDN

Inside Portable Stimulus: UVM Integration

Integrating Portable Stimulus Standard (PSS) capabilities with the Universal Verification Methodology (UVM) is not the same as an integration between two languages. In our previous column, Aileen ...