EDN

Symphony EDA rolls out VHDL simulator

SAN FRANCISCO — Hardware description language (HDL) simulation provider Symphony EDA has introduced VHDL Simili 3.0, a VHDL simulation environment that the company claims reduces verification cycle ...
Hackaday

Pulse: A New VHDL Simulator

With VHDL being arguably more deterministic and bullet-proof than Verilog, it’s good to see another open source VHDL simulator joining the fray that is not a variation of ghdl. Written by [Óscar ...
EDN

Ansoft approves VHDL-AMS models for use with simulator

Ansoft reports that it has certified the VHDL-AMS models from the FAT-AK30 working group of the German Association of the Automotive Industry (Verband der Automobilindustrie, VDA) to run in Simplorer, ...
Design-Reuse

Synopsys speeds Verilog, VHDL simulation

MOUNTAIN VIEW, Calif. — Claiming substantial speedups in its Verilog and VHDL simulation products, Synopsys Inc. this week is announcing releases of its VCS Verilog and Scirocco VHDL simulators. The ...