Mentor Graphics is exploring the application of formal verification techniques in an FPGA design flow. Formal verification is recognized in the application-specific integrated circuit (ASIC) market as ...

Over a third of all high-end ASIC designers now use FPGAs for prototyping 500,000-plus-gate designs. Driving this trend is the fact that a median application-specific integrated-circuit (ASIC) design ...

Time-saving verification tools have been added to an advanced tool flow for high-end FPGA design. The flow, a collaboration between Xilinx Inc. of San Jose and Synopsys Inc. of Mountain View, Calif., ...

When you think about it, logic synthesis is a vital but rather intimidating part of modern chip design. This process takes a high-level description of intended functionality, written in an RTL ...

FPGA design starts are on the rise due to the lower startup costs and re-programmability that FPGA devices can provide. However, large, complex FPGA devices pose significant challenges to an FPGA ...

Recently, Brian Bailey organized a round table that resulted in a two-part article called Supporting CPUs Plus FPGAs. The experts discussed the evolving reality of systems design based on FPGAs and ...

The more we know about the bigger picture, context, historical and projected trends, or simply how other people do the same thing we do, the more efficiently and successfully we can do our specific ...