Ars Technica

4T SRAM, 6T SRAM, EDRAM, DRAM, and 1T-SRAM for CPUs

These are various forms of local, on-chip memory. Except for the DRAM. 4T (4 transistor) SRAM takes up 4 times the space that regular DRAM does 1T-SRAM seems to be a hybrid of DRAM that allows for ...
Design-Reuse

Renesas Technology Develops Technique that Overcomes Effects of Threshold Variation to Stabilize the Operation of Embedded SRAM built with 65nm Process

High yield achieved for the world's smallest level 6-transistor SRAM memory-cell area (0.494µm 2) ; stabilization technique addresses variability of transistor characteristics. Tokyo, June 15, 2006 −− ...
EDN

Renesas memory cell mixes SRAM, DRAM tech

Tokyo – Renesas Technology Corp. has developed a new SRAM memory cell structure that combines SRAM and DRAM technologies. The device is about half the size of a conventional SRAM cell, but still has ...
EDN

Record SRAM Size, Non-Conventional Lithography, New Tunneling Transistor Highlight the Late-News Topics to be Covered at 2009 IEEE International Electron Devices Meeting

Record SRAM Size, Non-Conventional Lithography, New Tunneling Transistor Highlight the Late-News Topics to be Covered at 2009 IEEE International Electron Devices Meeting BALTIMORE, MD (October 26, ...
Design-Reuse

Low Power 7T SRAM Cell Scheme - ''Saving Write Zero Power''

This paper presents a Seven-transistor SRAM cell intended for the advanced microprocessor. A low power write scheme, which reduces SRAM power by using seven-transistor sense-amplifying memory cell, ...